WRITE THE CODE IN VERILOG: Instead of using Registers, USE D FLIP FLOPS and a clock....

Stale díograin olol Joo Toot nay Sale apet react * Be Given 3 D-Bep flops named A, QC input Outpute ZI, 20. let D-flip flops are having inpeet D-A, D-B, 0-c and outputs A.EC. - State table present states Input Flip flop inputs) outputs А в с Next states 근 이 DA OLD_C 01 ooi Too DE ☺ 010 001 oo! loo - Det all as don't cares unused States be taken (0.1,6,7,10,11,12,13,14,15) €

21-EM (3,4,5,8,9) D_A = Em (3.4) D-B = Em (3,9) Đọc = f ( $8) 22= Em ( 2,3, 819) * k-map Simplification 5 O OLH10 AB too ol X X au DA= 5 x + CX = X 0-B = A + CX CX 1 O-CE ARBY 1 [21= A + B t ex 21 - [email protected]+ x x x 22 - A+

Circuit diagram using D-flipflops DA A FE2 - clocks Verilog module for state Machine Averillog module for D-flip flop Code module DFF ( input clk , D, reset, Output reg a); always @ (posedge clic or negedge reset) begin if (reset) qiz i'bo; else qC=D; end

endmodule // verlog module-top level module ber State machine I using three D-feipflops modele State - machine ll Input port declarations fput clk, x, reset, I output port declarations output 2274 ) ; Il combinational logic for D-flipflop inputs for Flipflop inputs and outputs Il Internal signal declaratione wire Det, CBI PEC, A,B,C ; assign DAA = {w¢ ^ 1)); assign D-B = ((A & X) 1 & 2))); assign D-CF ((A & (vx) | (8&x)) ; Il D-flip flop an stærstations DFF D-A Cock (ck), D(-A),. reset (reset), -9(A)); DFF D-2 (-cckck), .01008),.

Reset (reset), -9(B)); Off D3 (ccok (cm), D (0-c) ,- recet (veset), 9(0)); Ii Combination al logéc for State Machine outputs assfagn 22. = (AIC); assign 21 = (Al Bl (C&x)) ; endmodule