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I need help plz 6. 4-stage MIPS pipeline: It has "IF, ID-EX, MEM, WB" stages. Specify...

Question:

I need help plz

6. 4-stage MIPS pipeline: It has IF, ID-EX, MEM, WB stages. Specify how many stalls (or bubbles) are required for the follo

6. 4-stage MIPS pipeline: It has "IF, ID-EX, MEM, WB" stages. Specify how many stalls (or bubbles) are required for the following cases. Assume that there is a forwarding logic and branch condition is determined at ID-EX stage. No delayed branch is assumed. (a) lw $1, 4($0) add $2, $1, $1 (b) lw $1, 4($0) beq $1, $2, add $3, $4, $5 X: sub $3, $3, $5 7. For problem 2 (c), how many bubbles are generated in the total cycles if we use 5-stage pipelining. Assume that there is a forwarding logic, the branch is determined at ID stage, the delayed branch is considered, and we do not use branch prediction. Among the bubbles, how many bubbles are caused by data hazard and by control hazard, respectively. Optimize your code to minimize the bubbles by rescheduling the code.

Answers

We a stage MIPS pipeline clock instruction des 2 3 43 7 8 g ID EX MEMI WB $1 4( $0) IF add $2 $1 $1 ID IF Stall MEM WB EX Nom

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