Answers
given that clock rate = 1GHZ = 10^9 HZ means 1 clock time = 1/ 10^9 second = 1nanosecond
given that non pipelined take 9 cycle means non pipeline take 9* 1nanosecond = 9 nanoesecond to excute a instruction.
1) since there is no specific clock rate gien for pipelined processor
so clock cycle time remain same for pipeline as non pipeline
similarly clock rate is remain same for pipeline as non pipeline
so clock cycle time = 1nanoseocnd for pipeline and non pipeline both
and clock rate = 1GHZ for pipeline and non pipeline
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2)
a pipeline version of this processor has 5 stege with time = 2.0 ns, 1,5ns, 1.0ns , 2.6ns, 1.9ns
each stage require 0.4ns extra for buffer
so effective time of 5 stage = 2.4ns , 1.9ns, 1.4ns , 3ns, 2.3ns
in pipeline all stage operate in parallel so overall time to take execute 1 instruction = maximum of all 5 stage time
= max { 2.4, 1.9, 1.4, 3.0 ,2.3 } = 3nanosecond
so execution time for single instruction in pipeline processor = 3nanosecond
It is 3 times faster than non pipelined processor .so it take only 33.33% time as compared to non pipeline faster .
so it is 300% time faster than non pipelin processor .
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3)
speed up = time taken to execute 1 instruction in non pipeline manner / time taken to execute 1 instruction in non pipeline manner
speed up = 9/3 = 3
so speed up over the non-pipelined processor = 3
Ideally speed up = number of stage = 5
so throughput = practically achieved speed up / Ideally speed up
= 3/5 = 0.6
= 60%
the maximum throughput of the pipelined processor expressed as MIPS is 60%
.