3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive...

Question:

3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive 3-bit modulo-6 (0,1,2,3,4,5) counter (see Table 3). The design has one input named Dir and three outputs named B2, B1 and BO. The outputs (B2, B1 and BO) are dependent upon being in the present state only. After each clock pulse, when Dir is at logic "O', the outputs (B2, B1, BO) step through the count sequence in following order:- 0,1,2,3,4,5. After each clock pulse, when Dir is at logic "l'", the outputs (B2, B1, BO) step through the count sequence in following order:-5,4,3,2,1,0. Question 3 continues on the next page. 6E5Z1101_EC Page 5/8 Question 3 continued Table 3 Modulo-s Count sequence Count B2 B1 BO 0 0 0 1 1 0 0 1 2 3 4 5 OOO OO 0 0 0 1 1 (a) Draw the state diagram for the circuit described in Q3. (3 marks) (b) Create a state table for the state diagram for answer 23-la). (3 marks) (c) Update the state table for answer 03-(b) to include assigned state values and take account of any unused states. (5 marks) (d) Determine the size of the ROM required for the design. (2 marks) Determine the ROM's addresses (identify and include signal names) (2 marks) Determine the ROM's data (identify and include signal names). le) (f) 12 marks)

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